Rider does not use maximum processors in my PC

Avatar
19980ductri
Created

I can only set the maximum processors to 8, I have 72 logical processors (I use dual xeon e5 2696v3, 32c 72t), but Rider does not let me set it to maximum core count in my PC
I also used task manager but it would not help at all

Votes

0

Share

19 comments
Avatar
19980ductri
Created

Please help me 

 

0
Avatar
Dmitry Kazantsev
Created

Hello,

Thank you for contacting Rider support. 

What is the maximum value available in the “Use up to processes in parallel” dropdown? (please scroll to the bottom)

Also, would you mind sharing Rider logs with us?

You can collect it via Help | Collect Logs and Diagnostic Data. Please upload the archive to the Upload service and let me know the Upload ID. 

Have a nice day!

0
Avatar
Dmitry Kazantsev
Created
Additional note: I just noticed that you develop Unreal Engine project. The setting we are talking about doesn't affect the number of processes to use for UE compilation. It is calculated by UBT itself and depends on the available free RAM and CPU architecture.
If you want UBT to build your project with 72 processes you would need 108GB (1.5GB*72) of free RAM.
0
Avatar
19980ductri
Created

I have like over 30gbs of free ram, so it should have been more than just maximum 8 processes that could be used

0
Avatar
Dmitry Kazantsev
Created
Hello,

Thank you for the details shared.
Would you mind sharing Rider logs with us, please?
0
Avatar
19980ductri
Created

How can I send the log folder? I have zipped it but cannot send here

0
Avatar
Dmitry Kazantsev
Created
Please upload it to the Upload Service (https://uploads.jetbrains.com/) and let me know the Upload ID.
0
Avatar
19980ductri
Created

Here is the upload ID of the log zipped folder: 2024_05_29_JfR6amViFiTe9J5dDJPD5k

0
Avatar
Dmitry Kazantsev
Created

Thank you! This value is determined by value of Environment.ProcessorCount. Please check the following:

  • The value of DOTNET_PROCESSOR_COUNT environment variable;
  • The value of NUMBER_OF_PROCESSORS environment variable;
  • Create a new project and verify the output of: Console.WriteLine("Environment.ProcessorCount: "+ Environment.ProcessorCount); 

Please let me know the results.

0
Avatar
19980ductri
Created

It says I have 64 processors

0
Avatar
19980ductri
Created

but still it only takes into account 8 processes maximum

0
Avatar
19980ductri
Created

hi, I have some more updates, sometimes, I can set the max parallel processes to 64, sometimes, it's only 8. I used a dual xeon e5 2969v3 PC which has 36 cores and 72 threads in total.
The task manager also shows that my PC has 2 NUMA nodes (NUMA0 has 64 logical processors and NUMA1 has the other 8)
I don't know if this has something to do with the issue but hopefully this will help you, thanks

0
Avatar
Dmitry Kazantsev
Created

Thank you for keeping me posted and sharing additional information. It looks interesting. 

I assume it might be related to these threads on github:

I have some more questions and steps you can try.

  • Did you notice, is there any difference in how you are running Rider in these two scenarios (when Rider allows selecting 64 or 8)?
  • Did you, by chance, adjust Processor Affinity for the ToolBox or for the explorer.exe processes?

I assume in your case, OS defines which processors group to use. In case OS selects group 0, you see 64 in Rider settings. In other case, Rider shows only 8 available.

To verify this, please try to launch Rider from cmd forcing it to run on different NUMA nodes:

1. on NUMA node 0. Then check what value you can set in Rider settings. I assume it would allow to select maximum 64 processors in the dropdown.

cd {RiderInstallPath}/bin
start /NODE 0 ./rider64.exe

2. Then close Rider and run in on second NUMA node. In this case, I assume the maximum value 8 would be available in the dropdown.

cd {RiderInstallPath}/bin
start /NODE 1 ./rider64.exe

Please let me know the outcome.
Have a nice day!

0
Avatar
19980ductri
Created

Hi, I have tried your solutions and thanks fully it works.
But, I notice some weird behaviors:
1/ When I tried opening rider64.exe with NODE0 (64 processes in total) → this results in Rider can only use 8 processors max
2/ After that tried NODE1 (which has the other 8) → now I can choose 64 processes max in parallel

You can see in the picture I use NODE1 and the result is belo

0
Avatar
19980ductri
Created
0
Avatar
Dmitry Kazantsev
Created
That is interesting. Unfortunately, something went wrong and you didn't attach a screenshot. 
Maybe we mixed up NUMA node IDs. Would you mind trying to run coreinfo.exe from sysinternals (https://learn.microsoft.com/en-us/sysinternals/downloads/coreinfo) from terminal and sharing the output?
0
Avatar
Dmitry Kazantsev
Created

Additional note:

You might want to try using the workaround mentioned on Github: https://github.com/dotnet/runtime/issues/29686

Open terminal, and set temporary environment variables. Then launch Rider from the same terminal session

set complus_GCCpuGroup=1
set COMPlus_Thread_UseAllCpuGroups=1
{RiderInstallPath}/bin/rider64.exe
0
Avatar
19980ductri
Created

Hi, my issue is now temporarily resolved, I could now use all 72 processors, but only when using cmd like instructions above
This is the coreinfo.txt that I have run like you told me to

Intel(R) Xeon(R) CPU E5-2696 v3 @ 2.30GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000043
HTT           *    Hyperthreading enabled
CET           -    Supports Control Flow Enforcement Technology
Kernel CET    -    Kernel-mode CET Enabled
User CET      -    User-mode CET Allowed
HYPERVISOR    -    Hypervisor is present
VMX           *    Supports Intel hardware-assisted virtualization
SVM           -    Supports AMD hardware-assisted virtualization
X64           *    Supports 64-bit mode

SMX           *    Supports Intel trusted execution
SKINIT        -    Supports AMD SKINIT
SGX           -    Supports Intel SGX

NX            *    Supports no-execute page protection
SMEP          *    Supports Supervisor Mode Execution Prevention
SMAP          -    Supports Supervisor Mode Access Prevention
PAGE1GB       *    Supports 1 GB large pages
PAE           *    Supports > 32-bit physical addresses
PAT           *    Supports Page Attribute Table
PSE           *    Supports 4 MB pages
PSE36         *    Supports > 32-bit address 4 MB pages
PGE           *    Supports global bit in page tables
SS            *    Supports bus snooping for cache operations
VME           *    Supports Virtual-8086 mode
RDWRFSGSBASE    *    Supports direct GS/FS base access

FPU           *    Implements i387 floating point instructions
MMX           *    Supports MMX instruction set
MMXEXT        -    Implements AMD MMX extensions
3DNOW         -    Supports 3DNow! instructions
3DNOWEXT      -    Supports 3DNow! extension instructions
SSE           *    Supports Streaming SIMD Extensions
SSE2          *    Supports Streaming SIMD Extensions 2
SSE3          *    Supports Streaming SIMD Extensions 3
SSSE3         *    Supports Supplemental SIMD Extensions 3
SSE4a         -    Supports Streaming SIMDR Extensions 4a
SSE4.1        *    Supports Streaming SIMD Extensions 4.1
SSE4.2        *    Supports Streaming SIMD Extensions 4.2

AES           *    Supports AES extensions
AVX           *    Supports AVX instruction extensions
AVX2          *    Supports AVX2 instruction extensions
AVX-512-F     -    Supports AVX-512 Foundation instructions
AVX-512-DQ    -    Supports AVX-512 double and quadword instructions
AVX-512-IFAMA    -    Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF    -    Supports AVX-512 prefetch instructions
AVX-512-ER    -    Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD    -    Supports AVX-512 conflict detection instructions
AVX-512-BW    -    Supports AVX-512 byte and word instructions
AVX-512-VL    -    Supports AVX-512 vector length instructions
FMA           *    Supports FMA extensions using YMM state
MSR           *    Implements RDMSR/WRMSR instructions
MTRR          *    Supports Memory Type Range Registers
XSAVE         *    Supports XSAVE/XRSTOR instructions
OSXSAVE       *    Supports XSETBV/XGETBV instructions
RDRAND        *    Supports RDRAND instruction
RDSEED        -    Supports RDSEED instruction

CMOV          *    Supports CMOVcc instruction
CLFSH         *    Supports CLFLUSH instruction
CX8           *    Supports compare and exchange 8-byte instructions
CX16          *    Supports CMPXCHG16B instruction
BMI1          *    Supports bit manipulation extensions 1
BMI2          *    Supports bit manipulation extensions 2
ADX           -    Supports ADCX/ADOX instructions
DCA           *    Supports prefetch from memory-mapped device
F16C          *    Supports half-precision instruction
FXSR          *    Supports FXSAVE/FXSTOR instructions
FFXSR         -    Supports optimized FXSAVE/FSRSTOR instruction
MONITOR       *    Supports MONITOR and MWAIT instructions
MOVBE         *    Supports MOVBE instruction
ERMSB         *    Supports Enhanced REP MOVSB/STOSB
PCLMULDQ      *    Supports PCLMULDQ instruction
POPCNT        *    Supports POPCNT instruction
LZCNT         *    Supports LZCNT instruction
SEP           *    Supports fast system call instructions
LAHF-SAHF     *    Supports LAHF/SAHF instructions in 64-bit mode
HLE           -    Supports Hardware Lock Elision instructions
RTM           -    Supports Restricted Transactional Memory instructions

DE            *    Supports I/O breakpoints including CR4.DE
DTES64        *    Can write history of 64-bit branch addresses
DS            *    Implements memory-resident debug buffer
DS-CPL        *    Supports Debug Store feature with CPL
PCID          *    Supports PCIDs and settable CR4.PCIDE
INVPCID       *    Supports INVPCID instruction
PDCM          *    Supports Performance Capabilities MSR
RDTSCP        *    Supports RDTSCP instruction
TSC           *    Supports RDTSC instruction
TSC-DEADLINE    *    Local APIC supports one-shot deadline timer
TSC-INVARIANT    *    TSC runs at constant rate
xTPR          *    Supports disabling task priority messages

EIST          *    Supports Enhanced Intel Speedstep
ACPI          *    Implements MSR for power management
TM            *    Implements thermal monitor circuitry
TM2           *    Implements Thermal Monitor 2 control
APIC          *    Implements software-accessible local APIC
x2APIC        *    Supports x2APIC

CNXT-ID       -    L1 data cache mode adaptive or BIOS

MCE           *    Supports Machine Check, INT18 and CR4.MCE
MCA           *    Implements Machine Check Architecture
PBE           *    Supports use of FERR#/PBE# pin

PSN           -    Implements 96-bit processor serial number

PREFETCHW     *    Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).
Maximum implemented address width: 48 bits (virtual), 46 bits (physical).

Processor signature: 000306F2

Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**--------------------------------------------------------------
--------
Physical Processor 1 (Hyperthreaded):
--**------------------------------------------------------------
--------
Physical Processor 2 (Hyperthreaded):
----**----------------------------------------------------------
--------
Physical Processor 3 (Hyperthreaded):
------**--------------------------------------------------------
--------
Physical Processor 4 (Hyperthreaded):
--------**------------------------------------------------------
--------
Physical Processor 5 (Hyperthreaded):
----------**----------------------------------------------------
--------
Physical Processor 6 (Hyperthreaded):
------------**--------------------------------------------------
--------
Physical Processor 7 (Hyperthreaded):
--------------**------------------------------------------------
--------
Physical Processor 8 (Hyperthreaded):
----------------**----------------------------------------------
--------
Physical Processor 9 (Hyperthreaded):
------------------**--------------------------------------------
--------
Physical Processor 10 (Hyperthreaded):
--------------------**------------------------------------------
--------
Physical Processor 11 (Hyperthreaded):
----------------------**----------------------------------------
--------
Physical Processor 12 (Hyperthreaded):
------------------------**--------------------------------------
--------
Physical Processor 13 (Hyperthreaded):
--------------------------**------------------------------------
--------
Physical Processor 14 (Hyperthreaded):
----------------------------**----------------------------------
--------
Physical Processor 15 (Hyperthreaded):
------------------------------**--------------------------------
--------
Physical Processor 16 (Hyperthreaded):
--------------------------------**------------------------------
--------
Physical Processor 17 (Hyperthreaded):
----------------------------------**----------------------------
--------
Physical Processor 18 (Hyperthreaded):
------------------------------------**--------------------------
--------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**------------------------
--------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**----------------------
--------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**--------------------
--------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**------------------
--------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**----------------
--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**--------------
--------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**------------
--------
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**----------
--------
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**--------
--------
Physical Processor 28 (Hyperthreaded):
--------------------------------------------------------**------
--------
Physical Processor 29 (Hyperthreaded):
----------------------------------------------------------**----
--------
Physical Processor 30 (Hyperthreaded):
------------------------------------------------------------**--
--------
Physical Processor 31 (Hyperthreaded):
--------------------------------------------------------------**
--------
Physical Processor 32 (Hyperthreaded):
----------------------------------------------------------------
**------
Physical Processor 33 (Hyperthreaded):
----------------------------------------------------------------
--**----
Physical Processor 34 (Hyperthreaded):
----------------------------------------------------------------
----**--
Physical Processor 35 (Hyperthreaded):
----------------------------------------------------------------
------**

Logical Processor to Socket Map:
Socket 0:
************************************----------------------------
--------
Socket 1:
------------------------------------****************************
********

Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************************************************
--------
NUMA Node 1:
----------------------------------------------------------------
********
Calculating Cross-NUMA Node Access Cost...                                           
Approximate Cross-NUMA Node Access Cost (relative to fastest):
    00  01
00: 1.4 1.2
01: 1.1 1.0

Logical Processor to Cache Map:
Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------------------------------------------------------
--------
Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------------------------------------------------------
--------
Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
**--------------------------------------------------------------
--------
Unified Cache       1, Level 3,   45 MB, Assoc  20, LineSize  64
************************************----------------------------
--------
Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------------------------------------------------------
--------
Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------------------------------------------------------
--------
Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
--**------------------------------------------------------------
--------
Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------------------------------------------------------
--------
Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------------------------------------------------------
--------
Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
----**----------------------------------------------------------
--------
Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------------------------------------------------------
--------
Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------------------------------------------------------
--------
Unified Cache       4, Level 2,  256 KB, Assoc   8, LineSize  64
------**--------------------------------------------------------
--------
Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------------------------------------------------------
--------
Instruction Cache   4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------------------------------------------------------
--------
Unified Cache       5, Level 2,  256 KB, Assoc   8, LineSize  64
--------**------------------------------------------------------
--------
Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----------------------------------------------------
--------
Instruction Cache   5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----------------------------------------------------
--------
Unified Cache       6, Level 2,  256 KB, Assoc   8, LineSize  64
----------**----------------------------------------------------
--------
Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--------------------------------------------------
--------
Instruction Cache   6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--------------------------------------------------
--------
Unified Cache       7, Level 2,  256 KB, Assoc   8, LineSize  64
------------**--------------------------------------------------
--------
Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**------------------------------------------------
--------
Instruction Cache   7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**------------------------------------------------
--------
Unified Cache       8, Level 2,  256 KB, Assoc   8, LineSize  64
--------------**------------------------------------------------
--------
Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**----------------------------------------------
--------
Instruction Cache   8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**----------------------------------------------
--------
Unified Cache       9, Level 2,  256 KB, Assoc   8, LineSize  64
----------------**----------------------------------------------
--------
Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**--------------------------------------------
--------
Instruction Cache   9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**--------------------------------------------
--------
Unified Cache      10, Level 2,  256 KB, Assoc   8, LineSize  64
------------------**--------------------------------------------
--------
Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**------------------------------------------
--------
Instruction Cache  10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**------------------------------------------
--------
Unified Cache      11, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------**------------------------------------------
--------
Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**----------------------------------------
--------
Instruction Cache  11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**----------------------------------------
--------
Unified Cache      12, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------**----------------------------------------
--------
Data Cache         12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**--------------------------------------
--------
Instruction Cache  12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**--------------------------------------
--------
Unified Cache      13, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------**--------------------------------------
--------
Data Cache         13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**------------------------------------
--------
Instruction Cache  13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**------------------------------------
--------
Unified Cache      14, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------**------------------------------------
--------
Data Cache         14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**----------------------------------
--------
Instruction Cache  14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**----------------------------------
--------
Unified Cache      15, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------**----------------------------------
--------
Data Cache         15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**--------------------------------
--------
Instruction Cache  15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**--------------------------------
--------
Unified Cache      16, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------**--------------------------------
--------
Data Cache         16, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------**------------------------------
--------
Instruction Cache  16, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------**------------------------------
--------
Unified Cache      17, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------**------------------------------
--------
Data Cache         17, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------**----------------------------
--------
Instruction Cache  17, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------**----------------------------
--------
Unified Cache      18, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------**----------------------------
--------
Data Cache         18, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------**--------------------------
--------
Instruction Cache  18, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------**--------------------------
--------
Unified Cache      19, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------**--------------------------
--------
Unified Cache      20, Level 3,   45 MB, Assoc  20, LineSize  64
------------------------------------****************************
--------
Data Cache         19, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------**------------------------
--------
Instruction Cache  19, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------**------------------------
--------
Unified Cache      21, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------**------------------------
--------
Data Cache         20, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------**----------------------
--------
Instruction Cache  20, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------**----------------------
--------
Unified Cache      22, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------**----------------------
--------
Data Cache         21, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------**--------------------
--------
Instruction Cache  21, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------**--------------------
--------
Unified Cache      23, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------**--------------------
--------
Data Cache         22, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------**------------------
--------
Instruction Cache  22, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------**------------------
--------
Unified Cache      24, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------**------------------
--------
Data Cache         23, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------**----------------
--------
Instruction Cache  23, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------**----------------
--------
Unified Cache      25, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------**----------------
--------
Data Cache         24, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------**--------------
--------
Instruction Cache  24, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------**--------------
--------
Unified Cache      26, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------------**--------------
--------
Data Cache         25, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------**------------
--------
Instruction Cache  25, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------**------------
--------
Unified Cache      27, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------------**------------
--------
Data Cache         26, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------**----------
--------
Instruction Cache  26, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------**----------
--------
Unified Cache      28, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------**----------
--------
Data Cache         27, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------**--------
--------
Instruction Cache  27, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------**--------
--------
Unified Cache      29, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------------------**--------
--------
Data Cache         28, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------------**------
--------
Instruction Cache  28, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------------**------
--------
Unified Cache      30, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------------------**------
--------
Data Cache         29, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------**----
--------
Instruction Cache  29, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------**----
--------
Unified Cache      31, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------------**----
--------
Data Cache         30, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------------**--
--------
Instruction Cache  30, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------------**--
--------
Unified Cache      32, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------------------------**--
--------
Data Cache         31, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------------------**
--------
Instruction Cache  31, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------------------**
--------
Unified Cache      33, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------------------------**
--------
Data Cache         32, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
**------
Instruction Cache  32, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
**------
Unified Cache      34, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
**------
Unified Cache      35, Level 3,   45 MB, Assoc  20, LineSize  64
----------------------------------------------------------------
********
Data Cache         33, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
--**----
Instruction Cache  33, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
--**----
Unified Cache      36, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
--**----
Data Cache         34, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
----**--
Instruction Cache  34, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
----**--
Unified Cache      37, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
----**--
Data Cache         35, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
------**
Instruction Cache  35, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
------**
Unified Cache      38, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------------------
------**

Logical Processor to Group Map:
Group 0:
****************************************************************
--------
Group 1:
----------------------------------------------------------------
********
 

0
Avatar
Dmitry Kazantsev
Created

Thank you for keeping  me posted.  As I understand this issue is fixed in Windows 11 (Account for availability of multiple processor groups on Windows 11+).

At the moment I see the following available options:

  • To set the mentioned environment variables globally per your user, so that it will always be active;
  • Make a rider.bat file that sets the env variables and runs rider. So that you can start Rider via this script;
  • Update to Windows 11;

Hope I was helpful. If there is anything else I can assist you with, please let me know.

Have a nice day!

 

0

Please sign in to leave a comment.